Circuits for Low Power Digital Signal Processing

It is predicted that at the 90nm technolony node, leakage power will surpass dynamic power. This poses several challenges to high-speed circuit designers. By the same token, the complexity of low power, low operating frequency designs is threatened more and more by static power dissipation concerns. It has been recently shown that if energy per operation (EOP) is used as an optimization metric, then for a given microarchitecture, an optimal choice of Vdd exists. However, throughput constraints are considered in this design only a-posteriori, and are not included in the optimization problem. In this project, we aim to extend these results, bringing architectural considerations into the game. The design and implementation of a digital filter, running at frequencies in the 1-10 MHz range, to be used as a decimator in a sigma-delta modulator, will be used as a case study. Different architectural solutions (FIR, IIR, serial) will be compared from the point of view of the optimal-EOP Vdd point, the goal being to design a filter architecture that can run at the optimal EOP point, while at the same time meeting the required throughput constraints. In addition, we will also investigate scalability of such attempt as we increase the operating frequency beyond the 110Mhz range.